SH-2A Datasheet, PDF (274/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.4.59
STS
Store from
System Register
STore System register
System Control Instruction
Format
STS MACH,Rn
STS MACL,Rn
STS PR,Rn
STS.L MACH,@–Rn
STS.L MACL,@–Rn
STS.L PR,@–Rn
Abstract
MACH → Rn
MACL → Rn
PR → Rn
Rn – 4 → Rn, MACH → (Rn)
Rn – 4 → Rn, MACL → (Rn)
Rn – 4 → Rn, PR → (Rn)
Code
Cycle
0000nnnn00001010 1
0000nnnn00011010 1
0000nnnn00101010 1
0100nnnn00000010 1
0100nnnn00010010 1
0100nnnn00100010 1
T Bit
—
—
—
—
—
—
Description
Stores data from system register MACH, MACL, or PR into a specified destination.
Operation
STSMACH(long n) /* STS MACH,Rn */
{
R[n]=MACH;
PC+=2;
}
STSMACL(long n) /* STS MACL,Rn */
{
R[n]=MACL;
PC+=2;
}
STSPR(long n) /* STS PR,Rn */
{
R[n]=PR;
PC+=2;
}
STSMMACH(long n) /* STS.L MACH,@–Rn */
{
R[n]–=4;
Rev. 3.00 Jul 08, 2005 page 260 of 484
REJ09B0051-0300