SH-2A Datasheet, PDF (18/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 2 Programming Model
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0
R0^*1
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15, SP (hardware stack pointer)^*2
Notes: 1. R0 functions as an index register in the indirect indexed
register addressing mode and indirect indexed GBR
addressing mode. In some instructions, R0 functions as
a fixed source register or destination register.
2. R15 functions as a hardware stack pointer (SP) during
exception processing.
Figure 2.2 General Registers
Rev. 3.00 Jul 08, 2005 page 4 of 484
REJ09B0051-0300