SH-2A Datasheet, PDF (108/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.3.4
BLD
Bit Load
Bit LoaD
Bit Manipulation Instruction
SH-2A/SH2A-FPU (New)
Format
Abstract
Code
Cycle
BLD.B #imm3, @(disp12,Rn) (<imm> of (disp+Rn)) → T 0011nnnn0iii10010011dddddddddddd 3
BLD #imm3, Rn
<imm> of Rn → T
10000111nnnn1iii
1
T Bit
Operation
result
Operation
result
Description
Stores a specified bit of memory at the address indicated by (disp + Rn), or of the LSB 8 bits of a
general register Rn, in the T bit. The bit number is specified by 3-bit immediate data. With the
BLD.B instruction, data is read from memory as a byte unit.
BLD.B #imm3, @(disp12, Rn)
Specified by #imm3
7
0
(disp+Rn)
BLD #imm3, Rn
31
Rn
T
Lower 8 bits specified
by #imm3
7
0
T
Rev. 3.00 Jul 08, 2005 page 94 of 484
REJ09B0051-0300