SH-2A Datasheet, PDF (360/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(2) When the succeeding instruction writes to the destination register or flag of the preceding
instruction. (However, contention only occurs if an instruction other than a multiply
instruction, divide instruction, LDBANK instruction, RESBANK instruction, MOVMU
instruction, or MOVML instruction writes to registers and flags other than the FPU register
and CS bit. No contention is detected with a multiply instruction, divide instruction, LDBANK
instruction, or RESBANK instruction. In addition, contention is only detected for Rn with the
MOVMU instruction and for R0 with the MOVML instruction. No contention occurs if either
of these instructions write to other registers.) (Figures 8.20 to 8.25)
ADD R3,R4
MOV R5,R4
IF ID EX
IF — ID EX
Figure 8.20 Example of Contention Due to Instruction that Overwrites Destination of
Preceding Instruction 1
MOV.L @R0,R1
MOV.L @R2,R1
IF ID EX MA
IF — — ID EX
Figure 8.21 Example of Contention Due to Instruction that Overwrites Destination of
Preceding Instruction 2
CLIPS.B R3
CLIPS.B R4
IF ID EX
IF ID EX
Figure 8.22 Example of No Contention in Case of CS Bit
MOV
MULR
R5,R6
R0,R6
IF ID EX
IF ID mm mm mm WB
Figure 8.23 Example of MULR No Contention
MOV R5,R6
MOVMU.L@R15+,R13
IF ID EX
IF ID EX MA MA MA WB
Figure 8.24 Example of MOVMU.L No Contention
Rev. 3.00 Jul 08, 2005 page 346 of 484
REJ09B0051-0300