SH-2A Datasheet, PDF (185/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.4.9
Section 6 Instruction Descriptions
BSR
Branch to SubRoutine
Branch to Subroutine Procedure
Branch Instruction
Delayed Branch Instruction
Format
BSR label
Abstract
PC → PR, disp × 2+ PC → PC
Code
Cycle T Bit
1011dddddddddddd 2
—
Description
Branches to the subroutine procedure at a specified address. The PC value is stored in the PR, and
the program branches to an address specified by PC + displacement. However, in this case it is
used for address calculation. The PC is the address 4 bytes after this instruction. The 12-bit
displacement is sign-extended and doubled. Consequently, the relative interval from the branch
destination is –4096 to +4094 bytes. If the displacement is too short to reach the branch
destination, the JSR instruction must be used instead. With JSR, the destination address must be
transferred to a register by using the MOV instruction. This BSR instruction and the RTS
instruction are used together for a subroutine procedure call.
Note
Since this is a delayed branch instruction, the instruction after BSR is executed before branching.
No interrupts and address errors are accepted between this instruction and the next instruction. If
the next instruction is a branch instruction, it is acknowledged as an illegal slot instruction.
Operation
BSR(long d) /* BSR disp */
{
long disp;
if ((d&0x800)==0) disp=(0x00000FFF & (long) d);
else disp=(0xFFFFF000 | (long) d);
PR=PC+Is_32bit_Inst(PR+2);
PC=PC+(disp<<1);
Delay_Slot(PR+2);
}
Rev. 3.00 Jul 08, 2005 page 171 of 484
REJ09B0051-0300