SH-2A Datasheet, PDF (221/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.4.28
MAC.L
Multiply and ACcumulate
Long
Double-Precision
Multiply-and-Accumulate
Operation
Arithmetic Instruction
Format
MAC.L @Rm+, @Rn+
Abstract
Signed operation,
(Rn) × (Rm) + MAC → MAC
Code
Cycle
0000nnnnmmmm1111 4
T Bit
—
Description
Does signed multiplication of 32-bit operands obtained using the contents of general registers Rm
and Rn as addresses. The 64-bit result is added to contents of the MAC register, and the final
result is stored in the MAC register. Every time an operand is read, they increment Rm and Rn by
four.
When the S bit is cleared to 0, the 64-bit result is stored in the coupled MACH and MACL
registers. When bit S is set to 1, addition to the MAC register is a saturation operation of 48 bits
starting from the LSB. For the saturation operation, only the lower 48 bits of the MACL register
are enabled and the result is limited to a range of H'FFFF800000000000 (minimum) and
H'00007FFFFFFFFFFF (maximum).
Operation
MACL(long m,long n) /* MAC.L @Rm+,@Rn+*/
{
unsigned long RnL,RnH,RmL,RmH,Res0,Res1,Res2;
unsigned long temp0,templ,temp2,temp3;
long tempm,tempn,fnLmL;
tempn=(long)Read_Long(R[n]);
R[n]+=4;
tempm=(long)Read_Long(R[m]);
R[m]+=4;
if ((long)(tempn^tempm)<0) fnLmL=-1;
else fnLmL=0;
Rev. 3.00 Jul 08, 2005 page 207 of 484
REJ09B0051-0300