SH-2A Datasheet, PDF (390/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
Type
Category
Number Execution
of Stages States
Latency
Contention
Instructions
Double- Floating-
6
precision point
floating- register-
point
register
instructions transfer
instructions
2
1 • These instruc- FMOV DRm,DRn
tions use the
FPU load/store
pipeline.
Floating-
5
point
register-
immediate
instructions
Floating-
6
point
register
load
instructions
1
4 • These instruc- FCNVSD FPUL,DRn
tions use the
FPU arithmetic
FCNVDS DRm,FPUL
operation
pipeline.
2
0/2/3/4^*4 • These instruc- FMOV.D @Rm,DRn
1/2/3/4^*4
0/2/3/4^*4
tions use the
FPU load/store
pipeline and
FMOV.D @Rm+,DRn
FMOV.D @(R0,Rm),DRn
memory access
pipeline.
• This is 32-bit
instruction.
FMOV.D @(disp12,Rm),DRn
• This instruction
uses the FPU
load/store
pipeline and
memory access
pipeline.
Floating-
5
point
register
store
instructions
2
0 • These instruc- FMOV.D DRm,@Rn
1/0^*3
tions use the
FPU load/store
FMOV.D DRm,@-Rn
0
pipeline and
FMOV.D DRm,@ (R0,Rn)
memory access
pipeline.
• This is 32-bit
instruction.
FMOV.D DRm,@(disp12,Rn)
• This instruction
uses the FPU
load/store
pipeline and
memory access
pipeline.
Rev. 3.00 Jul 08, 2005 page 376 of 484
REJ09B0051-0300