SH-2A Datasheet, PDF (432/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(3) Unconditional Branch Instructions
Instruction Types
BRA
BRAF
BSR
BSRF
JMP
JSR
RTS
label
Rm
label
Rm
@Rm
@Rm
Pipeline
Instruction A
Delay slot
Instruction after next
Second instruction
after next
Branch destination
instruction
↔ ↔ ↔ ↔ ↔ Slots
IF ID EX
IF — — ID EX ⋅ ⋅ ⋅
IF ⋅ ⋅ ⋅ (Fetched but discarded)
IF ⋅ ⋅ ⋅ (Fetched but discarded)
— IF ID EX ⋅ ⋅ ⋅
Operation
The pipeline ends after three stages: IF, ID, EX. Unconditional branch instructions are delayed
branch instructions.
The branch destination address is calculated in the EX stage. The instruction after the
unconditional branch instruction (instruction A) – that is, the delay slot instruction – is not
discarded after being fetched, as with a conditional branch instruction, but is executed. However,
the ID stage of this delay slot instruction is stalled for a 2-slot interval. The branch destination
instruction fetch is started from the slot following the instruction A EX stage slot.
Interrupts are not accepted in the delay slot.
Instruction Issuance
These instructions use the branch pipeline.
If an instruction fetch has not yet been performed for the instruction (delay slot) immediately
following one of these instructions, execution of that instruction is delayed.
Rev. 3.00 Jul 08, 2005 page 418 of 484
REJ09B0051-0300