SH-2A Datasheet, PDF (352/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
EX
Shift pipeline
EX
Branch pipeline
mm mm WB _{Multiplier pipeline}
Preceding
instruction ^IF
Succeeding _IF
instruction
EX
MA WB _{Memory access pipeline}
ID
EX
Integer pipeline 1
ID
EX
Integer pipeline 2
CPU
FPU
DF
EX
NA
SF
FPU load/store pipeline
DF
E1
E2
SF
FPU arithmetic operation pipeline
ED
FPU division/square root extraction pipeline
Priority allocation (always allocated)
Normal allocation (allocated if free)
Figure 8.1 SH-2A/SH2A-FPU Pipelines
Instruction 1
Instruction 2
Instruction 3
Instruction 4
Instruction 5
Instruction 6
↔ ↔ ↔ ↔ ↔ ↔ ↔ : Slots
IF ID EX MA WB
IF ID EX
IF ID EX MA WB
IF ID EX
IF ID EX
IF ID EX MA WB
    →
Time
Figure 8.2 Basic Pipeline Configuration
Instruction
stream
Rev. 3.00 Jul 08, 2005 page 338 of 484
REJ09B0051-0300