SH-2A Datasheet, PDF (450/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(b) When an STS.L instruction is immediately followed by a MULS.W, MULU.W, DMULS.L,
DMULU.L, MUL.L, MULR, STS (register). STS.L (memory), or LDS (register) instruction
As the STS.L instruction does not lock the multiplier, parallel execution is performed.
STS.L MACL,@-Rn
MUL.L Rm,Rn
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA
IF ID mm mm
IF ID EX ⋅ ⋅ ⋅
(c) When an STS.L instruction is immediately followed by a STS (register) or STS.L (memory)
instruction.
Parallel execution is not possible, as contention occurs with the multiplication result read bus.
STS.L MACH,@-Rn
STS.L MACL,@-Rn
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA
IF — ID EX MA
IF ID EX ⋅ ⋅ ⋅
(d) When an STS.L instruction is immediately followed by an LDS.L (memory) instruction
Memory access pipeline contention occurs and parallel execution is not possible.
STS.L MACH,@-Rn
LDS.L @Rn+,MACL
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA
IF — ID EX MA WB
IF ID EX ⋅ ⋅ ⋅
Instruction Issuance
These instructions use the memory access pipeline.
These instructions use the multiplier, but do not lock it.
These instructions use the multiplication result read path.
Parallel Execution Capability
No particular comments
Rev. 3.00 Jul 08, 2005 page 436 of 484
REJ09B0051-0300