SH-2A Datasheet, PDF (252/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.4.43 OR
Logical OR
OR logical
Logical Instruction
Format
OR Rm,Rn
OR #imm,R0
OR.B #imm,@(R0,GBR)
Abstract
Rn | Rm → Rn
R0 | imm → R0
(R0 + GBR) | imm → (R0 + GBR)
Code
0010nnnnmmmm1011
11001011iiiiiiii
11001111iiiiiiii
Cycle
1
1
3
T Bit
—
—
—
Description
Logically ORs the contents of general registers Rn and Rm, and stores the result in Rn. The
contents of general register R0 can also be ORed with zero-extended 8-bit immediate data, or 8-bit
memory data accessed by using indirect indexed GBR addressing can be ORed with 8-bit
immediate data.
Operation
OR(long m,long n) /* OR Rm,Rn */
{
R[n]|=R[m];
PC+=2;
}
ORI(long i)
{
/* OR #imm,R0 */
R[0]|=(0x000000FF & (long)i);
PC+=2;
}
ORM(long i) /* OR.B #imm,@(R0,GBR) */
{
long temp;
temp=(long)Read_Byte(GBR+R[0]);
temp|=(0x000000FF & (long)i);
Write_Byte(GBR+R[0],temp);
PC+=2;
}
Rev. 3.00 Jul 08, 2005 page 238 of 484
REJ09B0051-0300