SH-2A Datasheet, PDF (486/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
Operation
• Single-Precision
The CPU pipeline ends after three stages – IF, ID, EX – and the FPU pipeline after 13 stages –
IF, DF, E1, ED, ED, ED, ED, ED, ED, ED, E1, E2, SF. That is to say, after one E1 stage has
been performed, the ED stage is repeated 7 times, followed by E1, E2, and SF.
• Double-Precision
The CPU pipeline ends after three stages – IF, ID, EX – and the FPU pipeline after 26 stages –
IF, DF, E1, E1, ED, ED, ED, ED, ED, ED, ED, ED, ED, ED, ED, ED, ED, ED, ED, ED, ED,
E1, E1, E1, E2, SF. That is to say, after the E1 stage has been performed twice, the ED stage
is repeated 17 times, followed by E1, E1, E1, E2, and SF.
The contention described in section 8.6, Contention Due to FPU, occurs. If there is an
overlapping instruction that accesses the FSQRT result register in the FSQRT pipeline, that
instruction is kept waiting until execution of the FSQRT instruction is finished. Stages from E1
onward are stalled until the end of FSQRT execution, and subsequent instructions are also subject
to stalling. Therefore, if a floating-point instruction that uses the FSQRT result register, or an
FPU-related CPU instruction, is not located within 19 instructions immediately after the FSQRT
instruction in the case of single-precision, or 47 instructions in the case of double-precision, a
CPU instruction or another FPU instruction can be executed during that interval, enabling
performance to be improved.
Instruction Issuance
These instructions use the FPU arithmetic operation pipeline. See section 8.6, Contention Due to
FPU, for details of contention.
The ED stages of these instructions operate in states, without regard to slots.
Parallel Execution Capability
No particular comments
Rev. 3.00 Jul 08, 2005 page 472 of 484
REJ09B0051-0300