SH-2A Datasheet, PDF (451/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(12) RTE Instruction
Instruction Type
RTE
Pipeline
Instruction A
Delay slot
Branch destination
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA MA EX EX EX
IF — — — — — ID EX ⋅ ⋅ ⋅
IF — ID EX ⋅ ⋅ ⋅
Operation
The pipeline ends after eight stages: IF, ID, EX, MA, MA, EX, EX, EX. RTE is a delayed branch
instruction. The ID stage of the delay slot instruction is stalled for a 5-slot interval. The IF stage
of the branch destination instruction is started from the slot after the second MA stage of RTE.
Instruction Issuance
This instruction does not cause resource contention.
Parallel Execution Capability
This is a multi-cycle instruction, and cannot be executed in parallel with a subsequent instruction.
Rev. 3.00 Jul 08, 2005 page 437 of 484
REJ09B0051-0300