SH-2A Datasheet, PDF (285/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.4.66
TST
AND Operation
T Bit Setting
TeST logical
Section 6 Instruction Descriptions
Logical Instruction
Format
Abstract
Code
Cycle T Bit
TST Rm,Rn
Rn & Rm, when result is 0, 1 → T 0010nnnnmmmm1000 1
Test
results
TST #imm,R0 R0 & imm, when result is 0, 1 → T 11001000iiiiiiii 1
Test
results
TST.B #imm,
(R0 + GBR) & imm, when result is 11001100iiiiiiii 3
@(R0,GBR) 0, 1 → T
Test
results
Description
Logically ANDs the contents of general registers Rn and Rm, and sets the T bit to 1 if the result is
0 or clears the T bit to 0 if the result is not 0. The Rn data does not change. The contents of general
register R0 can also be ANDed with zero-extended 8-bit immediate data, or the contents of 8-bit
memory accessed by indirect indexed GBR addressing can be ANDed with 8-bit immediate data.
The R0 and memory data do not change.
Operation
TST(long m,long n) /* TST Rm,Rn */
{
if ((R[n]&R[m])==0) T=1;
else T=0;
PC+=2;
}
TSTI(long i) /* TEST #imm,R0 */
{
long temp;
temp=R[0]&(0x000000FF & (long)i);
if (temp==0) T=1;
else T=0;
PC+=2;
}
TSTM(long i) /* TST.B #imm,@(R0,GBR) */
Rev. 3.00 Jul 08, 2005 page 271 of 484
REJ09B0051-0300