SH-2A Datasheet, PDF (138/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.3.19 MOV
MOVe structure data
Structure Data Transfer
Data Transfer Instruction
SH-2A/SH2A-FPU (New)
Format
MOV.B Rm, @(disp12,Rn)
MOV.W Rm, @(disp12,Rn)
MOV.L Rm, @(disp12,Rn)
MOV.B @(disp12,Rm), Rn
MOV.W @(disp12,Rm), Rn
MOV.L @(disp12,Rm), Rn
Abstract
Code
Rm → (disp+Rn)
0011nnnnmmmm00010000dddddddddddd
Rm → (disp×2+Rn) 0011nnnnmmmm00010001dddddddddddd
Rm → (disp×4+Rn) 0011nnnnmmmm00010010dddddddddddd
(disp+Rm) → sign
extension → Rn
0011nnnnmmmm00010100dddddddddddd
(disp×2+Rm) → sign 0011nnnnmmmm00010101dddddddddddd
extension → Rn
(disp×4+Rm) → Rn 0011nnnnmmmm00010110dddddddddddd
Cycle T Bit
1
―
1
―
1
―
1
―
1
―
1
―
Description
Transfers a source operand to a destination. This instruction is ideal for data access in a structure
or the stack.
Note
For the Renesas Technology Super H RISC engine assembler, declarations should use scaled
values (×1, ×2, ×4) as displacement values.
Operation
MOVBS12 (long d, long m, long n)
{
long disp;
/* MOV.B Rm, @(disp12,Rn) */
disp = (0x00000FFF & (long)d);
Write_Byte(R[n]+disp,R[m]);
PC+=4;
}
MOVWS12 (long d, long m, long n)
{
long disp;
/* MOV.W Rm, @(disp12,Rn) */
disp = (0x00000FFF & (long)d);
Rev. 3.00 Jul 08, 2005 page 124 of 484
REJ09B0051-0300