SH-2A Datasheet, PDF (374/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
8.7 Contention Due to Multiplier
Multiply instructions, multiply-and-accumulate instructions, and instructions that manipulate the
registers for these instructions (MACH, MACL) use the multiplier. In addition, the STS FPUL,Rn,
and STS FPSCR,Rn instructions use the multiplication result read bus. Details of pipelining and
contention are given below, with instructions divided into the categories shown. The numbers
immediately following the instructions, in the form (A/B/C), indicate (number of execution
slots/latency/number of lock slots).
• Multiply-and-accumulate instructions
MAC.L (4/6/5)
IF ID EX MA MA mm mm mm
MAC.W (3/5/4)
IF ID EX MA MA mm mm
• Multiply instructions (I)
DMUL.S, DMUL.U, MUL.L (2/3/2) IF ID mm mm mm
MULS.W, MULU.W(1/2/1)
IF ID mm mm
• Multiply instructions (II) (register return)
MULR (2/4/2)
IF ID mm mm mm WB
• Register write instructions (I)
CLRMAC, LDS (1/2/1)
IF ID mm mm
• Register write instructions (II)
LDS.L (1/3/2)
IF ID EX MA WB
• Register read instructions (including STS FPUL,Rn and STS FPSCR,Rn)
STS (1/2/0)
IF ID EX WB
STS.L (1/2/0)
IF ID EX MA
Facts about Contention
Contention arises with multi-cycle instructions in the same way as with general instructions
(figure 8.51). See section 8.3.4, Details of Contention Due to Multi-Cycle Instruction, for details.
MAC.L @R1+,@R2+ IF ID EX MA MA mm mm mm
MAC.L @R3+,@R4+ IF — — — ID EX MA MA mm mm mm
Note: MAC.L is an instruction with an execution rate of 4.
Figure 8.51 Example of Multi-Cycle Instructions Using Multiplier
The following rules apply to instructions that use the multiplier.
Rev. 3.00 Jul 08, 2005 page 360 of 484
REJ09B0051-0300