SH-2A Datasheet, PDF (380/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
Type
Category
Number Execution
of Stages States
Latency
Contention
Instructions
Data
Memory
5
transfer load
instructions instructions
1
2 • These instruc- MOV.W @(disp,PC),Rn
tions use the
memory access
MOV.L
@(disp,PC),Rn
pipeline.
MOV.B @Rm,Rn
MOV.W @Rm,Rn
MOV.L @Rm,Rn
MOV.B @Rm+,Rn
MOV.W @Rm+,Rn
MOV.L @Rm+,Rn
MOV.B @-Rm,R0
MOV.W @-Rm,R0
MOV.L @-Rm,R0
MOV.B @(disp,Rm),R0
MOV.W @(disp,Rm),R0
MOV.L @(disp,Rm),Rn
MOV.B @(R0,Rm),Rn
MOV.W @(R0,Rm),Rn
MOV.L @(R0,Rm),Rn
MOV.B @(disp,GBR),R0
MOV.W @(disp,GBR),R0
MOV.L @(disp,GBR),R0
5 to 20 1 to 16 2 to 17
MOVML.L @R15+,Rn
MOVMU.L @R15+,Rn
5
1
2 • These are 32-bit MOV.B @(disp12,Rm),Rn
instructions.
MOV.W @(disp12,Rm),Rn
• These instruc-
tions use the
MOV.L
@(disp12,Rm),Rn
memory access MOVU.B @(disp12,Rm),Rn
pipeline.
MOVU.W @(disp12,Rm),Rn
Rev. 3.00 Jul 08, 2005 page 366 of 484
REJ09B0051-0300