SH-2A Datasheet, PDF (446/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(b) When an LDS.L instruction is immediately followed by a MULS.W, MULU.W, DMULS.L,
DMULU.L, MUL.L, MULR, STS (register). STS.L (memory), or LDS (register) instruction
As the LDS.L instruction locks the multiplier, stalling occurs a further 1-slot interval back.
LDS.L @Rm+,MACH
STS MACL,Rn
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA WB
IF — — ID EX WB
IF — ID EX ⋅ ⋅ ⋅
(c) When an LDS.L instruction is immediately followed by an LDS.L (memory) instruction
Execution is delayed for an LDS.L instruction execution state (1-slot) interval.
LDS.L @Rn+,MACH
LDS.L @Rn+,MACL
Instruction after next
↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA WB
IF — ID EX MA WB
IF ID EX ⋅ ⋅ ⋅
Instruction Issuance
These instructions use the memory access pipeline.
These instructions use the multiplier.
These instructions are executed if there is a remaining multiplication lock interval of 1.
These instructions lock the multiplier for a 2-slot interval.
Parallel Execution Capability
No particular comments
Rev. 3.00 Jul 08, 2005 page 432 of 484
REJ09B0051-0300