SH-2A Datasheet, PDF (376/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
MULR1 lock interval
MULR1 R0,R1
MAC.L @R3+,@R4+
← →
IF ID mm mm mm WB
IF — ID EX MA MA mm mm mm
Figure 8.56 Example of No Multiplier Lock Contention when Following Instruction is
Multiply-and-Accumulate Instruction
If the following instruction is an instruction in category “Register write instructions (II),” it is
executed when there is one slot remaining in the lock interval (figure 8.57).
MAC.L lock interval
Lock interval with
LDS.L instruction
MAC.L @R1+,@R2+
LDS.L @R3+,MACH
←→
←→
IF ID EX MA MA mm mm mm
IF — — — — ID EX MA WB
Figure 8.57 Example of Unlocking 1 State Earlier
STS and STS.L instructions do not lock the multiplier. Therefore, parallel execution is
possible for an STS instruction and MUL.L instruction, etc.
MUL.L R1,R2
IF ID mm mm mm
STS MACH,R3 IF — — ID EX WB
MUL.L R4,R5
IF — ID mm mm mm
STS MACL,R6
IF — — — ID EX WB
MULR R0,R7
IF — — ID mm mm mm WB
Figure 8.58 Example of Parallel Execution of STS Instruction and MUL.L Instruction
Rev. 3.00 Jul 08, 2005 page 362 of 484
REJ09B0051-0300