SH-2A Datasheet, PDF (87/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
(5) Multiplication Result Rn Storage Instruction
MULR
MULR performs a 32-bit x 32-bit multiplication, and stores the lower 32 bits of the result in a
general register Rn.
(6) Batch Division Instructions
DIVS, DIVU
These instructions perform batch 32-bit ÷ 32-bit division. The DIVU instruction performs
division of unsigned data, and the DIVS instruction performs division of signed data.
(7) Saturation Value Comparison Instructions
CLIPS, CLIPU
These instructions perform a comparison with a saturation value, and store the saturation upper-
limit value in a general register Rn if the general register Rn contents exceed the saturation upper-
limit value, or store the saturation lower-limit value in general register Rn if the general register
Rn contents are less than the saturation upper-limit value. Only byte and word saturation values
are supported.
(8) Barrel Shift Instructions
SHAD, SHLD
These instructions shift arbitrary bits. Two kinds of instructions are provided, for an arithmetic
shift and a logical shift.
(9) Multiple Register Save/Restore Instructions
MOVML, MOVMU
These instructions save a number of consecutive registers to memory, or restore a number of
consecutive registers from memory. It is possible to specify a general register Rn, and to save or
restore consecutive general registers higher than or lower than the specified Rn.
Rev. 3.00 Jul 08, 2005 page 73 of 484
REJ09B0051-0300