SH-2A Datasheet, PDF (435/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(5) Unconditional Branch Instructions with No Delay (JSR/N @@(disp,TBR))
Instruction Types
JSR/N @@(disp,TBR)
Pipeline
↔ ↔ ↔ ↔ ↔ Slots
Instruction A
IF ID EX MA EX
Next instruction
IF — ⋅ ⋅ ⋅ (Fetched but discarded)
Instruction after next
IF ⋅ ⋅ ⋅ (Fetched but discarded)
Second instruction
after next
IF ⋅ ⋅ ⋅ (Fetched but discarded)
Branch destination
instruction
— — — IF ID EX ⋅ ⋅ ⋅
Operation
The pipeline ends after five stages: IF, ID, EX, MA, EX. Condition determination is performed in
the ID stage. This is not a delayed branch instruction. The branch destination address is calculated
in the second EX stage. All overrun-fetched instructions up to that point are discarded. The branch
destination instruction fetch is started from the slot following the slot with the second EX of
instruction A.
Instruction Issuance
This instruction uses the branch pipeline.
This instruction uses the memory access pipeline.
Parallel Execution Capability
No particular comments
Rev. 3.00 Jul 08, 2005 page 421 of 484
REJ09B0051-0300