SH-2A Datasheet, PDF (290/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.5 Floating-Point Instructions and FPU-Related CPU Instructions
6.5.1
FABS
Floating-point ABSolute value
Floating-Point
Absolute Value
Floating-Point Instruction
PR Format
0
FABS FRn
1
FABS DRn
Abstract
|FRn| → FRn
|DRn| → DRn
Code
Cycle
1111nnnn01011101 1
1111nnn001011101 1
T Bit
—
—
Description
This instruction clears the most significant bit of the contents of floating-point register FRn/DRn
to 0, and stores the result in FRn/DRn.
The cause and flag fields in FPSCR are not updated.
Operation
void FABS (int n){
FR[n] = FR[n] & 0x7fffffff;
pc += 2;
}
/* Same operation is performed regardless of precision. */
Possible Exceptions:
None
Rev. 3.00 Jul 08, 2005 page 276 of 484
REJ09B0051-0300