SH-2A Datasheet, PDF (90/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
unsigned char Write_Byte (unsigned long Addr, unsigned long Data);
unsigned short Write_Word (unsigned long Addr, unsigned long Data);
unsigned int
Write_Int (unsigned long Addr, unsigned long Data);
unsigned long Write_Long (unsigned long Addr, unsigned long Data);
unsigned double Write_Quad (unsigned long Addr, unsigned long Data);
Data Data is written to address Addr using the respective size. A word write to other than a 2n address or a
longword write to other than a 4n address will be detected as an address error.
unsigned long Write_Bank_Long (unsigned long Add, unsigned long
Data);
Data Data is written to the register bank entry indicated by the contents of address Addr.
unsigned long
unsigned long
unsigned long
unsigned long
Respective registers
R[16];
SR, GBR, VBR, TBR;
MACH, MACL, PR;
PC;
struct BANK {
unsigned long Rn_BANK[15];
unsigned long GBR_BANK;
unsigned long MACH_BANK;
unsigned long MACL_BANK;
unsigned long PR_BANK;
unsigned long IVN;
};
BANK Register_Bank[512];
Register bank structure definition
(VTO: Interrupt vector table address offset)
struct SR0 {
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
long
long
long
long
long
long
long
dummy0:17;
BO0:1
CS0:1;
dummy1:3;
M0:1;
Q0:1;
I0:4;
Rev. 3.00 Jul 08, 2005 page 76 of 484
REJ09B0051-0300