SH-2A Datasheet, PDF (195/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.4.15 CMP/cond
Compare
CoMPare conditionally
Section 6 Instruction Descriptions
Arithmetic Instruction
Format
CMP/EQ
CMP/GE
Rm,Rn
Rm,Rn
CMP/GT Rm,Rn
CMP/HI Rm,Rn
CMP/HS Rm,Rn
CMP/PL Rn
CMP/PZ Rn
CMP/STR Rm,Rn
CMP/EQ #imm,R0
Abstract
When Rn = Rm, 1 → T
When signed and Rn ≥ Rm,
1→T
When signed and Rn > Rm,
1→T
When unsigned and Rn > Rm,
1→T
When unsigned and Rn ≥ Rm,
1→T
When Rn > 0, 1 → T
When Rn ≥ 0, 1 → T
When a byte in Rn equals
a byte in Rm, 1 → T
When R0 = imm, 1 → T
Code
0011nnnnmmmm0000
0011nnnnmmmm0011
Cycle
1
1
T Bit
Comparison result
Comparison result
0011nnnnmmmm0111 1
Comparison result
0011nnnnmmmm0110 1
Comparison result
0011nnnnmmmm0010 1
Comparison result
0100nnnn00010101 1
0100nnnn00010001 1
0010nnnnmmmm1100 1
Comparison result
Comparison result
Comparison result
10001000iiiiiiii 1
Comparison result
Description
Compares general register Rn data with Rm data, and sets the T bit to 1 if a specified condition
(cond) is satisfied. The T bit is cleared to 0 if the condition is not satisfied. The Rn data does not
change. The following eight conditions can be specified. Conditions PZ and PL are the results of
comparisons between Rn and 0. Sign-extended 8-bit immediate data can also be compared with
R0 by using condition EQ. Here, R0 data does not change. Table 6.1 shows the mnemonics for the
conditions.
Rev. 3.00 Jul 08, 2005 page 181 of 484
REJ09B0051-0300