SH-2A Datasheet, PDF (362/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
BAND.B #imm3, (disp12,Rn)
(Execution state 3)
BOR.B #imm3, (disp12,Rn)
IF ID EX MA EX
IF — ID EX MA EX
Figure 8.27 Execution Example for Successive 32-Bit Bit Manipulation Instructions
(6) Except for the cases listed in (5), multicycle 32-bit instructions cannot be executed in parallel
with the instruction on the line following them (figure 8.28).
BAND.B #imm3, (disp12,Rn)
(Execution state 3)
ADD #imm, Rn
IF ID EX MA EX
IF — — ID EX MA EX
Figure 8.28 Multicycle 32-Bit Instruction Execution Example
8.3.5 Details of Contention Due to 32-Bit Instruction
The following rules apply to execution of 32-bit instructions.
(1) Parallel execution is not possible when the preceding instruction is a 32-bit instruction (figure
8.29).
(2) When the succeeding instruction is a 32-bit instruction, the preceding instruction can be
executed but the succeeding instruction cannot (figure 8.29).
(3) The last slot of a multi-cycle instruction and a 32-bit instruction can be executed in parallel
(figure 8.26).
(4) Only in cases where the preceding instruction in the last slot is a multicycle 32-bit instruction
such as BAND.B, BANDNOT.B, BLD.B, BLDNOT.B, BOR.B, BORNOT.B, or BXOR, and
the instruction on the next line is BAND.B, BANDNOT.B, BLD.B, BLDNOT.B, BOR.B,
BORNOT.B, or BXOR, does parallel execution take place. Parallel execution does not occur
in combinations with any other instructions (figures 8.27 and 8.28).
(5) A 32-bit instruction cannot be executed unless IF has been completed for the upper 16 bits and
the lower 16 bits (figure 8.30).
Relevant examples are shown in figures 8.26 and 8.27.
Rev. 3.00 Jul 08, 2005 page 348 of 484
REJ09B0051-0300