SH-2A Datasheet, PDF (3/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Main Revisions for this Edition
Item
1.1 Features
Page
1
2.2.2 Control
5
Registers
(1) Status Register,
SR
3.1.1 Exception
16
Handling Types and
Priority
Table 3.1 Exception
Types and Priority
3.1.2 Exception
18
Handling Operation
(2) Address Error,
RAM Error, Register
Bank Error, Interrupt,
or Instruction
Exception Handling
3.3.1 Address Error 22
Sources
Table 3.5 Bus
Cycles and Address
Errors
3.6.3 Interrupt
26
Exception Handling
Revision (See Manual for Details)
Description amended
The SH-2A/SH2A-FPU is a 32-bit RISC (reduced instruction set
computer) microprocessor that is upward-compatible with the SH-
1, SH-2, and SH-2E at the object code level.
Description amended
(32-bit, initial value =0000 0000 0000 0000 00X0 00XX 1111
00XX)
Note amended
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR,
RTS, RTE,
BF/S, BT/S, BSRF, BRAF
.
Description amended
⋅⋅⋅ and the vector table address offset of the interrupt exception
handling to be executed,⋅⋅⋅
Table amended
Bus Cycle
Type
Bus Master
Data
CPU or
read/write DMAC
Bus Cycle Operation
Double longword data accessed from double
longword boundary
Double longword data accessed from other
than double longword boundary
Address Error
Occurrence
No error (normal)
Address error
Description amended
⋅⋅⋅ and the vector table address offset of the interrupt exception
handling to be executed,⋅⋅⋅
Rev. 3.00 Jul 08, 2005 page iii of xiv