SH-2A Datasheet, PDF (375/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(1) Execution of a instruction that uses a multiplication result as its source is delayed by an
interval equivalent to the latency of that instruction (figure 8.52). If the following instruction
is one that reads MACH or MACL, execution is delayed by [latency – 1] cycled (figure 8.53).
If the following instruction is a multiply-and-accumulate instruction, execution is not delayed
(figure 8.54).
MULR R0,R4
ADD R4,R5
IF ID mm mm mm WB
IF — — — — ID EX WB
Figure 8.52 Example of Referencing Result Register Immediately after Multiplication (1)
MUL.L R2,R3
STS MACH,R4
IF ID mm mm mm
IF — — ID EX WB
Figure 8.53 Example of Referencing Result Register Immediately after Multiplication (2)
MAC.W @R1+,@R2+ IF ID EX MA MA mm mm
MAC.W @R3+,@R4+ IF — — ID EX MA MA mm mm
Figure 8.54 Example of Referencing Result Register Immediately after Multiplication (3)
(2) In the case of an instruction after an instruction that uses the multiplier, if the preceding
instruction locked the multiplier, execution is delayed until the multiplier is unlocked (figure
8.55).
MULR1 lock interval
MULR1 R0,R1
IF
MULR2 R0,R2
IF
← →
ID mm mm mm WB
— — ID mm mm mm WB
Figure 8.55 Example of Multiplier Lock Contention
However, if the following instruction is a multiply-and-accumulate instruction, it is executed
after waiting for the same kind of state interval as with an ordinary multi-cycle instruction,
rather than after waiting for the multiplier to be unlocked (figure 8.56).
Rev. 3.00 Jul 08, 2005 page 361 of 484
REJ09B0051-0300