SH-2A Datasheet, PDF (411/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(b) When a MULS.W instruction is immediately followed by a MULS.W, MULU.W, DMULS.L,
DMULU.L, MUL.L, MULR, STS (register). STS.L (memory), or LDS (register) instruction
As the MULS.W instruction locks the multiplier, parallel execution is not possible.
MULS.W Rm,Rn
STS
MACL,Rn
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID mm mm
IF — ID EX WB
IF ID EX ⋅ ⋅ ⋅
(c) When a MULS.W instruction is immediately followed by an LDS.L (memory) instruction
Parallel execution with the MULS.W instruction is not possible, as it locks the multiplier.
↔ ↔ ↔ ↔ ↔ ↔ Slots
MULS.W Rm,Rn
IF ID mm mm
LDS.L @Rn+,MACL IF — ID EX MA WB
Instruction after next
IF ID EX ⋅ ⋅ ⋅
Instruction Issuance
These instructions use the multiplier.
These instructions lock the multiplier for a 1-slot interval.
Parallel Execution Capability
No particular comments
Rev. 3.00 Jul 08, 2005 page 397 of 484
REJ09B0051-0300