SH-2A Datasheet, PDF (338/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
PC+=2;
}
Possible Exceptions:
• Address error
Examples
• STS
Example 1:
MOV.L #H'12ABCDEF, R12
LDS
R12, FPUL
STS
FPUL, R13
; After executing the STS instruction:
; R13 = 12ABCDEF
Example 2:
STS
FPSCR, R2
; After executing the STS instruction:
; The current content of FPSCR is stored in register R2
• STS.L
Example 1:
MOV.L #H'0C700148, R7
STS.L FPUL, @-R7
; Before executing the STS.L instruction:
; R7 = 0C700148
; After executing the STS.L instruction:
; R7 = 0C700144, and the content of FPUL is saved at memory
; location 0C700144.
Example 2:
MOV.L #H'0C700154, R8
STS.L FPSCR, @-R8
; After executing the STS.L instruction:
; The content of FPSCR is saved at memory location 0C700150.
Rev. 3.00 Jul 08, 2005 page 324 of 484
REJ09B0051-0300