SH-2A Datasheet, PDF (183/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.4.8
BRAF
BRAnch Far
Unconditional Branch
Format
BRAF Rm
Abstract
Rm + PC → PC
Section 6 Instruction Descriptions
Branch Instruction
Delayed Branch Instruction
Code
Cycle T Bit
0000mmmm00100011 2
—
Description
Branches unconditionally. The branch destination is PC + the 32-bit contents of the general
register Rm. However, in this case it is used for address calculation. The PC is the address 4 bytes
after this instruction.
Note
Since this is a delayed branch instruction, the instruction after BRAF is executed before
branching. No interrupts and address errors are accepted between this instruction and the next
instruction. If the next instruction is a branch instruction, it is acknowledged as an illegal slot
instruction.
Operation
BRAF(long m) /* BRAF Rm */
{
unsigned long temp;
temp=PC;
PC=PC+R[m];
Delay_Slot(temp+2);
}
Rev. 3.00 Jul 08, 2005 page 169 of 484
REJ09B0051-0300