SH-2A Datasheet, PDF (13/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

8.2 Slots and Pipeline Flow .................................................................................................... 339
8.3 Instruction Execution and Parallel Execution Capability ................................................. 341
8.3.1 Details of Resource Contention ........................................................................... 342
8.3.2 Details of Contention Due to Wait for Result of Previously Issued Instruction .. 345
8.3.3 Details of Register Contention and Flag Contention ........................................... 345
8.3.4 Details of Contention Due to Multi-Cycle Instruction......................................... 347
8.3.5 Details of Contention Due to 32-Bit Instruction.................................................. 348
8.3.6 Details of Contention Due to Instruction that Uses FPSCR ................................ 349
8.3.7 Details of Contention Due to Branch Instruction................................................. 350
8.4 Number of Instruction Execution States ........................................................................... 351
8.5 Effect of Memory Load Instruction on Pipeline ............................................................... 352
8.6 Contention Due to FPU..................................................................................................... 353
8.7 Contention Due to Multiplier............................................................................................ 360
8.8 Programming Strategy ...................................................................................................... 364
8.9 Pipeline Operations for Each Instruction .......................................................................... 364
8.9.1 Data Transfer Instructions ................................................................................... 378
8.9.2 Arithmetic Operation Instructions ....................................................................... 390
8.9.3 Logical Operation Instructions ............................................................................ 404
8.9.4 Shift Instructions.................................................................................................. 412
8.9.5 Branch Instructions.............................................................................................. 414
8.9.6 System Control Instructions................................................................................. 422
8.9.7 Exception Handling ............................................................................................. 443
8.9.8 Floating-Point Instructions and FPU-Related CPU Instructions.......................... 448
8.10 Simple Method of Calculating Required Number of Clock Cycles.................................. 475
Appendix A SH-2A/SH2A-FPU Parallel Execution................................................. 479
Appendix B Programming Guidelines (Using MOVI20 and MOVI20S) .......... 483
Rev. 3.00 Jul 08, 2005 page xiii of xiv