SH-2A Datasheet, PDF (399/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(7) Memory Store Instructions
Instruction Types
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
MOV.B
MOV.W
MOV.L
Rm,@Rn
Rm,@Rn
Rm,@Rn
Rm,@-Rn
Rm,@-Rn
Rm,@-Rn
R0,@Rn+
R0,@Rn+
R0,@Rn+
R0,@(disp,Rn)
R0,@(disp,Rn)
Rm,@(disp,Rn)
Rm,@(R0,Rn)
Rm,@(R0,Rn)
Rm,@(R0,Rn)
R0,@(disp,GBR)
R0,@(disp,GBR)
R0,@(disp,GBR)
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA
IF ID EX ⋅ ⋅ ⋅
IF ID EX ⋅ ⋅ ⋅
Operation
The pipeline ends after four stages: IF, ID, EX, MA. There is no WB stage as there is no return of
data to the register.
Instruction Issuance
These instructions use the memory access pipeline.
Rev. 3.00 Jul 08, 2005 page 385 of 484
REJ09B0051-0300