SH-2A Datasheet, PDF (441/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(6) STC.L Instructions
Instruction Types
STC.L
STC.L
STS.L
GBR,@-Rn
VBR,@-Rn
PR,@-Rn
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF ID EX MA
IF ID EX ⋅ ⋅ ⋅
IF ID EX ⋅ ⋅ ⋅
Operation
The pipeline ends after four stages: IF, ID, EX, MA.
Instruction Issuance
These instructions use the memory access pipeline.
Parallel Execution Capability
No particular comments
Rev. 3.00 Jul 08, 2005 page 427 of 484
REJ09B0051-0300