SH-2A Datasheet, PDF (27/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 2 Programming Model
2.4 Processing States
The CPU has five processing states: the reset state, exception handling state, bus-released state,
program execution state, and power-down state. Figure 2.5 shows the state transitions.
Power-on reset
from any state
Manual reset
from any state
Power-on reset state
Reset release
Manual reset state
Reset state
Interrupt or DMA address error
Exception-handling state
NMI or IRQ interrupt
Bus request
cleared
Bus
request
Bus-released state
Bus
request
cleared
Exception
handling
request
Bus
request
End of exception
handling
Program execution state
Bus request
Bus request
cleared
SLEEP
instruction with
STBY bit cleared
SLEEP
instruction with
STBY bit set
Sleep mode
Software standby mode
Hardware standby mode
Power-down state
Standby input from any state
Figure 2.5 Processing State Transitions
Rev. 3.00 Jul 08, 2005 page 13 of 484
REJ09B0051-0300