SH-2A Datasheet, PDF (64/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 5 Instruction Set
Classification
Branch
instructions
System control
instructions
Instruction
Type
Op Code
10
BF
BT
BRA
BRAF
BSR
BSRF
JMP
JSR
RTS
RTV/N
14
CLRT
CLRMAC
LDBANK
LDC
LDS
NOP
RESBANK
RTE
SETT
SLEEP
STBANK
STC
STS
TRAPA
Function
Number of
Instructions
Conditional branch, delayed
15
conditional branch (branches if T = 0)
Conditional branch, delayed
conditional branch (branches if T = 1)
Unconditional delayed branch
Unconditional delayed branch
Delayed branch to subroutine
procedure
Delayed branch to subroutine
procedure
Unconditional delayed branch
Branch to subroutine procedure,
delayed branch to subroutine
procedure
Return from subroutine procedure,
delayed return from subroutine
procedure
Return from subroutine procedure with
Rm → R0 transfer
T bit clear
36
MAC register clear
Register restoration from specified
register bank entry
Load into control register
Load into system register
No operation
Register restoration from register bank
Return from exception handling
T bit setting
Transition to power-down state
Register save to specified register
bank entry
Store from control register
Store from system register
Trap exception handling
Rev. 3.00 Jul 08, 2005 page 50 of 484
REJ09B0051-0300