SH-2A Datasheet, PDF (118/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.3.9
BST
Bit Store
Bit STore
Bit Manipulation Instruction
SH-2A/SH2A-FPU (New)
Format
BST.B #imm3, @(disp12,Rn)
BST #imm3, Rn
Abstract
Code
T → (<imm> of (disp+Rn)) 0011nnnn0iii10010010dddddddddddd
T → <imm> of Rn
10000111nnnn0iii
Cycle
3
1
T Bit
―
―
Description
Transfers the contents of the T bit to a specified 1-bit location of memory at the address indicated
by (disp + Rn), or of the LSB 8 bits of a general register Rn. The bit number is specified by 3-bit
immediate data. With the BST.B instruction, after data is read from memory as a byte unit,
transfer from the T bit to the specified bit is executed, and the resulting data is then written to
memory as a byte unit.
BST.B #imm3, @(disp12, Rn)
Specified by #imm3
7
0
(disp+Rn)
T
BST #imm3, Rn
31
Rn
Lower 8 bits specified
by #imm3
7
0
T
Rev. 3.00 Jul 08, 2005 page 104 of 484
REJ09B0051-0300