SH-2A Datasheet, PDF (377/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(3) MULR instructions, STS instructions affecting MACH, MACL, FPUL, or FPSCR, and STS.L
instructions affecting MACH or MACL chare a result register read bus, causing resource
contention (MA and WB stages). Therefore, parallel execution is not possible for STS and
STS.L instructions (figure 8.59).
If an STS or STS.L is located immediately after a MULR instruction, WB stage contention
occurs in the same way, and execution of the STS or STS.L instruction is delayed by 3 cycles
(figure 8.60).
MUL.L R1,R2
IF ID mm mm mm
STS MACH,R3 IF — — ID EX WB
STS.L MACL,@-R4
IF — — ID EX MA
Figure 8.59 Example of Contention with STS and STS.L
MUL.L R1,R2
IF ID mm mm mm
MULR R0,R3
IF — — ID mm mm mm WB
STS MACH,R4
IF — — — — ID EX WB
Figure 8.60 Example of Contention between MULR and STS
Rev. 3.00 Jul 08, 2005 page 363 of 484
REJ09B0051-0300