SH-2A Datasheet, PDF (200/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.4.17 DIV0U
DIVide (step 0) as Unsigned
Initialization for Unsigned Division
Arithmetic Instruction
Format
DIV0U
Abstract
0 → M/Q/T
Code
Cycle T Bit
0000000000011001 1
0
Description
DIV0U is an initialization instruction for unsigned division. It finds the quotient by repeatedly
dividing in combination with the DIV1 or another instruction that divides for each bit after this
instruction. See the description given with DIV1 for more information.
Operation
DIV0U() /* DIV0U */
{
M=Q=T=0;
PC+=2;
}
Example: See DIV1.
Rev. 3.00 Jul 08, 2005 page 186 of 484
REJ09B0051-0300