SH-2A Datasheet, PDF (225/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.4.29
MAC.W
Multiply and
ACcumulate Word
Single-Precision
Multiply-and-Accumulate
Operation
Section 6 Instruction Descriptions
Arithmetic Instruction
Format
MAC.W @Rm+, @Rn+
MAC @Rm+, @Rn+
Abstract
With sign,
(Rn) × (Rm) + MAC → MAC
Code
Cycle T Bit
0100nnnnmmmm1111 3
—
Description
Does signed multiplication of 16-bit operands obtained using the contents of general registers Rm
and Rn as addresses. The 32-bit result is added to contents of the MAC register, and the final
result is stored in the MAC register. Rm and Rn data are incremented by 2 after the operation.
When the S bit is cleared to 0, the operation is 16 × 16 + 64 → 64-bit multiply and accumulate and
the 64-bit result is stored in the coupled MACH and MACL registers.
When the S bit is set to 1, the operation is 16 × 16 + 32 → 32-bit multiply and accumulate and
addition to the MAC register is a saturation operation. For the saturation operation, only the
MACL register is enabled and the result is limited to a range of H'80000000 (minimum) and
H'7FFFFFFF (maximum).
If an overflow occurs, the MACH register is set to H'00000001. The result is stored in the MACL
register. The result is limited to a value between H'80000000 (minimum) for overflows in the
negative direction and H'7FFFFFFF (maximum) for overflows in the positive direction.
Operation
MACW(long m,long n) /* MAC.W @Rm+,@Rn+*/
{
long tempm,tempn,dest,src,ans;
unsigned long templ;
tempn=(long)Read_Word(R[n]);
R[n]+=2;
tempm=(long)Read_Word(R[m]);
R[m]+=2;
Rev. 3.00 Jul 08, 2005 page 211 of 484
REJ09B0051-0300