SH-2A Datasheet, PDF (106/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.3.3
BCLR
Bit Clear
Bit CLeaR
Bit Manipulation Instruction
SH-2A/SH2A-FPU (New)
Format
Abstract
Code
Cycle
BCLR.B #imm3, @(disp12,Rn) 0 → (<imm> of (disp+Rn)) 0011nnnn0iii10010000dddddddddddd 3
BCLR #imm3, Rn
0 → <imm> of Rn
10000110nnnn0iii
1
T Bit
―
―
Description
Clears a specified bit of memory at the address indicated by (disp + Rn), or of the LSB 8 bits of a
general register Rn. The bit number is specified by 3-bit immediate data. With the BCLR.B
instruction, after data is read from memory as a byte unit, clearing of the specified bit is executed,
and the resulting data is then written to memory as a byte unit.
BCLR.B #imm3, @(disp12, Rn)
Specified by #imm3
7
0
(disp+Rn)
0
BCLR #imm3, Rn
31
Rn
Lower 8 bits specified
by #imm3
7
0
0
Rev. 3.00 Jul 08, 2005 page 92 of 484
REJ09B0051-0300