SH-2A Datasheet, PDF (16/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 1 Overview
Item
Floating-Point Unit
(FPU)
Features
• On-chip floating-point coprocessor
• Supports single-precision (32 bits) and double-precision (64 bits)
• Supports IEEE754-compliant data types and exceptions
• Two rounding modes: Round to Nearest and Round to Zero
• Handling of denormalized numbers: Truncation to zero
• Floating-point registers
 Sixteen 32-bit floating-point registers
(single-precision x 16 words or double-precision x 8 words)
 Two 32-bit floating-point system registers
• Supports FMAC (multiply and accumulate) instruction
• Supports FDIV (divide) and FSQRT (square root) instructions
• Supports FLDI0/FLDI1 (load constant 0/1) instructions
• Instruction execution times
 Latency (FMAC/FADD/FSUB/FMUL): 3 cycles (single-precision), 8
cycles (double-precision)
 Pitch (FMAC/FADD/FSUB/FMUL): 1 cycle (single-precision), 6
cycles (double-precision)
Note: FMAC is supported for single-precision only.
• Five-stage pipeline
Rev. 3.00 Jul 08, 2005 page 2 of 484
REJ09B0051-0300