SH-2A Datasheet, PDF (418/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
8.9.3 Logical Operation Instructions
(1) Register-Register Logical Operation Instructions
Instruction Types
AND Rm,Rn
AND #imm,R0
NOT Rm,Rn
OR
Rm,Rn
OR
#imm,R0
TST Rm,Rn
TST #imm,R0
XOR Rm,Rn
XOR #imm,R0
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ Slots
IF ID EX
IF ID EX ⋅ ⋅ ⋅
IF ID EX ⋅ ⋅ ⋅
Operation
The pipeline ends after three stages: IF, ID, EX. In the EX stage, the data operation is completed
via the ALU.
Instruction Issuance
These instructions do not cause resource contention.
Parallel Execution Capability
No particular comments
Rev. 3.00 Jul 08, 2005 page 404 of 484
REJ09B0051-0300