SH-2A Datasheet, PDF (387/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
Type
Category
Number Execution
of Stages States
Latency
Contention
Instructions
System TRAP
8
control
instruction
instructions _SLEEP
7
instruction
5
6
5
0
—
TRAPA #imm
—
SLEEP
FPU
FPU load
5
load/store instructions
instructions
1
1
—
LDS
Rm,FPUL
2 • These instruc- LDS.L @Rm+,FPUL
tions use the
memory access
pipeline.
FPSCR
5
load
instructions
1
3
—
LDS
Rm,FPSCR
3
• These instruc- LDS.L @Rm+,FPSCR
tions use the
memory access
pipeline.
FPUL store
4
instruction
(STS)
1
2 • This instruction STS
FPUL,Rn
uses the
multiplication
result read path.
FPUL store
4
instruction
(STS.L)
1
2 • This instruction STS.L FPUL,@-Rn
uses the
memory access
pipeline.
FPSCR
4
store
instruction
(STS)
1
2 • This instruction STS
FPSCR,Rn
uses the
multiplication
result read path.
FPSCR
4
store
instruction
(STS.L)
1
1 • This instruction STS.L FPSCR,@-Rn
uses the
memory access
pipeline.
Rev. 3.00 Jul 08, 2005 page 373 of 484
REJ09B0051-0300