SH-2A Datasheet, PDF (67/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 5 Instruction Set
Table 5.2 shows the format used in tables 5.3 to 5.8, which list instruction codes, operation, and
execution states in order by classification.
Table 5.2 Instruction Code Format
Item
Format
Explanation
Instruction
Rm:
Rn:
imm:
disp:
Source register
Destination register
Immediate data
Displacement^*1
Instruction code MSB ↔ LSB
mmmm: Source register
nnnn: Destination register
0000: R0
0001: R1
⋅
⋅
⋅
1111: R15
iiii:
Immediate data
dddd: Displacement
Operation
→, ←
Direction of transfer
(xx)
Memory operand
M/Q/T
Flag bits in the SR
&
Logical AND of each bit
|
Logical OR of each bit
^
Exclusive OR of each bit
~
Logical NOT of each bit
<<n
n-bit left shift
>>n
Execution cycles —
n-bit right shift
Value when no wait states are inserted^*2
T bit
—
Value of T bit after instruction is executed.
An em-dash (—) in the column means no change.
Notes: 1. Depending on the operand size, displacement is scaled ×1, ×2, or ×4. For details, see
section 5, Instruction Descriptions.
2. Instruction execution cycles: The execution cycles shown in the table are minimums.
The actual number of cycles may be increased when (1) contention occurs between
instruction fetches and data access, or (2) when the destination register of the load
instruction (memory → register) and the register used by the next instruction are the
same.
Rev. 3.00 Jul 08, 2005 page 53 of 484
REJ09B0051-0300