SH-2A Datasheet, PDF (182/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
Example:
BRA TRGET
ADD R0,R1
NOP
..........
TRGET:
; Branches to TRGET
; Executes ADD before branching
; ← The PC location is used to calculate the branch destination
address of the BRA instruction
; ← Branch destination of the BRA instruction
Note:
When a delayed branch instruction is used, the branching operation takes place after the
slot instruction is executed, but the execution of instructions (register update, etc.) takes
place in the sequence delayed branch instruction → delayed slot instruction. For example,
even if a delayed slot instruction is used to change the register where the branch
destination address is stored, the register content previous to the change will be used as the
branch destination address.
Rev. 3.00 Jul 08, 2005 page 168 of 484
REJ09B0051-0300