SH-2A Datasheet, PDF (9/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.3.4 BLD ........... Bit LoaD ...................................... Bit Manipulation Instruction ... 94
6.3.5 BLDNOT ... Bit LoaDNOT .............................. Bit Manipulation Instruction ... 96
6.3.6 BOR ........... Bit OR ......................................... Bit Manipulation Instruction ... 98
6.3.7 BORNOT ... Bit ORNOT ................................. Bit Manipulation Instruction ... 100
6.3.8 BSET ......... Bit SET ........................................ Bit Manipulation Instruction ... 102
6.3.9 BST ............ Bit STore ..................................... Bit Manipulation Instruction ... 104
6.3.10 BXOR ........ Bit exclusive OR ......................... Bit Manipulation Instruction ... 106
6.3.11 CLIPS ........ CLIP as Signed ............................ Arithmetic Instruction ............. 108
6.3.12 CLIPU ........ CLIP as Unsigned ........................ Arithmetic Instruction ............. 111
6.3.13 DIVS .......... DIVide as Signed ........................ Arithmetic Instruction ............. 113
6.3.14 DIVU ......... DIVide as Unsigned .................... Arithmetic Instruction ............. 114
6.3.15 FMOV ........ Floating-point MOVe .................. Floating-Point Instruction........ 115
6.3.16 JSR/N ......... Jump to SubRoutine with No delay slot
...................................................... Branch Instruction ................... 118
6.3.17 LDBANK ... LoaD register BANK .................. System Control Instruction...... 121
6.3.18 LDC ........... LoaD to Control register ............. System Control Instruction...... 123
6.3.19 MOV .......... MOVe structure data ................... Data Transfer Instruction......... 124
6.3.20 MOV .......... MOVe reverse stack .................... Data Transfer Instruction......... 127
6.3.21 MOVI20 .... MOVe Immediate 20bits data ..... Data Transfer Instruction......... 130
6.3.22 MOVI20S .. MOVe Immediate 20bits data and 8bits Shift left
...................................................... Data Transfer Instruction......... 131
6.3.23 MOVML.L MOVe Multi-register Lower part Data Transfer Instruction......... 133
6.3.24 MOVMU.L MOVe Multi-register Upper part Data Transfer Instruction......... 136
6.3.25 MOVRT ..... MOVe Reverse Tbit .................... Data Transfer Instruction......... 139
6.3.26 MOVU ....... MOVe structure data as Unsigned
...................................................... Data Transfer Instruction......... 140
6.3.27 MULR ........ MULtiply to Register .................. Arithmetic Instruction ............. 142
6.3.28 NOTT ........ NOT Tbit ..................................... Data Transfer Instruction......... 143
6.3.29 PREF .......... PREFetch data to cache ............... Data Transfer Instruction......... 144
6.3.30 RESBANK REStore from registerBANK ...... System Control Instruction...... 145
6.3.31 RTS/N ........ ReTurn from Subroutine with No delay slot
...................................................... Branch Instruction ................... 147
6.3.32 RTV/N ....... ReTurn to Value and from subroutine with No delay slot
...................................................... Branch Instruction ................... 148
6.3.33 SHAD ........ SHift Arithmetic Dynamically .... Shift Instruction ....................... 150
6.3.34 SHLD ......... SHift Logical Dynamically ......... Shift Instruction ....................... 152
6.3.35 STBANK ... STore register BANK .................. System Control Instruction...... 154
6.3.36 STC ............ STore Control register ................. System Control Instruction...... 156
6.4 SH-2E CPU Instructions................................................................................................... 157
6.4.1 ADD .......... ADD Binary ................................ Arithmetic Instruction ............. 157
6.4.2 ADDC ........ ADD with Carry .......................... Arithmetic Instruction ............. 158
Rev. 3.00 Jul 08, 2005 page ix of xiv