SH-2A Datasheet, PDF (371/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
Floating-point load/store
instruction (double-
precision)
(FMOV DR0,DR2)
(latency 1 → latency 2)
Next floating-point
arithmetic operation
instruction (double-
precision)
(FADD DR2,DR4)
IF DF EX NA SF
IF — — DF E1 E1 ⋅ ⋅ ⋅ E1 E2 SF
Figure 8.45 Example of 1-Latency Instruction Immediately Preceding
Double-Precision Arithmetic Operation
If the destination register of a double-precision arithmetic operation instruction is used as a source
register by the following instruction, if “n” of FRn is an odd number, latency will be reduced by 1
cycle (figure 8.46). However, latency will not be reduced if “n” of FRn is an even number (figure
8.47).
Floating-point arithmetic
operation instruction
(double-precision)
(FADD DR0,DR2)
(latency 8 → latency 7)
Next floating-point
load/store instruction
(single-precision)
(FMOV FR3,FR5)
IF DF E1 E1 E1 E1 E1 E1 E2 SF
IF — — — — — DF EX NA SF
Figure 8.46 Example of Latency Reduction with Double-Precision Arithmetic
Operation Instruction
Rev. 3.00 Jul 08, 2005 page 357 of 484
REJ09B0051-0300