SH-2A Datasheet, PDF (393/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
(2) Register-Register Transfer Instructions (20-Bit Immediate Value)
Instruction Types
MOVI20 #imm20,Rn
MOVI20S #imm20,Rn
Pipeline
Instruction A
Next instruction
Instruction after next
↔ ↔ ↔ ↔ ↔ Slots
IF ID EX
IF ID EX ⋅ ⋅ ⋅
IF ID EX ⋅ ⋅ ⋅
Operation
The pipeline ends after three stages: IF, ID, EX. In the EX stage, data transfer is performed via
the ALU.
Instruction Issuance
These instructions do not cause resource contention.
Parallel Execution Capability
These are 32-bit instructions, and cannot be used in parallel execution. (See section 8.3.5, Details
of Contention Due to 32-Bit Instruction.)
Rev. 3.00 Jul 08, 2005 page 379 of 484
REJ09B0051-0300