SH-2A Datasheet, PDF (22/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 2 Programming Model
Reference Name
In case of transfer instruction:
FPSCR.SZ = 0 FPSCR.SZ = 1
In case of arithmetic/logical instruction: _{FPSCR.PR = 0 FPSCR.PR = 1}
FR0
FR1
FR2
FR3
FR4
FR5
FR6
FR7
FR8
FR9
FR10
FR11
FR12
FR13
FR14
FR15
DR0
DR2
DR4
DR6
DR8
DR10
DR12
DR14
Figure 2.3 Floating-Point Registers
Programming Note:
The values of FPR0 to FPR15 are undefined after a reset.
Register Name
FPR0
FPR1
FPR2
FPR3
FPR4
FPR5
FPR6
FPR7
FPR8
FPR9
FPR10
FPR11
FPR12
FPR13
FPR14
FPR15
2.2.5 Floating-Point System Registers
(1) Floating-Point Communication Register, FPUL (32-bit, initial value = undefined)
Data transfers between an FPU register and CPU register are performed via FPUL.
(2) Floating-Point Status/Control Register, FPSCR (32-bit, initial value = H'0004 0001)
31
—
23 22 21 20 19 18 17
12 11
76
210
QIS — SZ PR DN
Cause
Enable
Flag
RM
Rev. 3.00 Jul 08, 2005 page 8 of 484
REJ09B0051-0300