SH-2A Datasheet, PDF (51/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 4 Instruction Features
4.2 Addressing Modes
Addressing modes effective address calculation by the CPU core are described below.
Table 4.7 Addressing Modes and Effective Addresses
Addressing Instruction
Mode
Format
Direct
Rn
register
addressing
Indirect
register
addressing
@Rn
Post-
increment
indirect
register
addressing
@Rn +
Pre-
decrement
indirect
register
addressing
@–Rn
Effective Addresses Calculation
The effective address is register Rn. (The operand is
the contents of register Rn.)
The effective address is the content of register Rn.
Rn
Rn
The effective address is the content of register Rn. A
constant is added to the content of Rn after the
instruction is executed. 1 is added for a byte
operation, 2 for a word operation, or 4 for a longword
operation.
Rn
Rn
Rn + 1/2/4 ₊
1/2/4
The effective address is the value obtained by
subtracting a constant from Rn. 1 is subtracted for a
byte operation, 2 for a word operation, or 4 for a
longword operation.
Rn
Rn 1/2/4
Rn 1/2/4
1/2/4
Formula
—
Rn
Rn
(After the
instruction is
executed)
Byte: Rn + 1
→ Rn
Word: Rn + 2
→ Rn
Longword:
Rn + 4 → Rn
Byte: Rn – 1
→ Rn
Word: Rn – 2
→ Rn
Longword:
Rn – 4 → Rn
(Instruction
executed with
Rn after
calculation)
Rev. 3.00 Jul 08, 2005 page 37 of 484
REJ09B0051-0300